State all equations or formulas used and show all work done in the calculations. Submit only your work and answers.
Question 1
A non-pipelined CPU with a clock frequency of 2 GHz has instruction latencies with relative frequencies of instructions as shown in the following table.
| Instruction Type | Instruction Latency | Relative Frequency |
| Loads | 5 | 30% |
| Stores | 4 | 15% |
| Branches | 3 | 10% |
| Jumps | 2 | 5% |
| ALU/Logic | 4 | 40% |
- Calculate the average CPI.
- Calculate the average instruction execution time (IET).
A pipelined version of the CPU adds 0.1 ns overhead.
- Calculate the average instruction execution time of the pipelined CPU.
- Calculate the speedup obtained with the pipelined CPU.
Question 2
Consider the code sequence shown in the box on the right. Each instruction is numbered for reference (I1 – I7). Assume execution on a 5-stage pipeline.
a.Make a list of the RAW (read after write) data hazards in the code sequence.Using the reference numbers, your list should state the two instructions associated with the hazard and the register on which the hazard exists.
- In your list of hazards, place an asterisk (*) in front of those that are resolved by data forwarding.
- Place a hash (#) mark in front of any hazards not resolved by data forwarding. If any exist, determine if the hazards can be resolved by reordering the code sequence and show the new sequence.
Question 3
The basic formula for calculating AMAT is
The time for a hit is equal to the hit rate * cache access (hit) time. Recall the miss rate is
1 – hit rate.
For a 2-level cache, the AMAT formula is expanded to
The following table defines the profile for a multilevel cache hierarchy with main memory.
| Memory Level | Hit Time | Hit Rate |
| L1 Cache | 0.5 ns | 80% |
| L2 Cache | 1.8 ns | 95% |
| L3 Cache | 4.2 ns | 98.5% |
| Main Memory | 70 ns | 100% |
Misses in all three levels of cache will eventually hit in the main memory.
- Derive the formula to calculate the AMAT for this multilevel cache design.
- Using the information in the table and the derived formula, calculate the average memory access time for this memory hierarchy.
Question 4
Using the code sequence in Question 2, create a pipeline diagram that shows the execution of the instructions by cycle. Example:
Be sure to indicate any stalls due to unresolved hazards if any exist.
How many cycles are required for the code to execute in the pipeline?
