Differential AmplifierDesign

In this assignment, you will design the microphone pre–amplifier highlighted with red in the block diagram, which is a differential amplifier as shown in the schematics below.

Your design should satisfy the required differential gain, input impedance, single–ended common–mode gain, and the power dissipation specifications provided in Section A below. Then in Sections B and C, you will simulate your circuit on LTSpice to compare the simulation results with hand calculations.

A. Hand design: Design the bipolar differential amplifier and the current source and bias network
(𝑅1, 𝑄3, 𝑎𝑛𝑑 𝑄4) above such that:
(i) Differential gain: 𝐴𝑑 ≥ 200 𝑉
𝑉,
(ii) Input differential resistance: 𝑅𝑖𝑑 ≥ 50 𝑘Ω,
(iii) 𝐴𝑐𝑚 < 0.1 where 𝐴𝑐𝑚 is the single–ended common–mode gain (the gain to a common–mode input signal when the output is measured not differentially but from one of the outputs with respect to ground).

(iv) To keep the battery discharge lifetime long, the power consumption of the differential amplifier, 𝑃𝑇𝑂𝑇𝐴𝐿, must be less than 2 milliwatts.
Design the circuit with BJTs having 𝛽 = 200, 𝑉𝐴 = 100 𝑉, 𝑎𝑛𝑑 𝑉𝐵𝐸 = ~0.7 𝑉 𝑖𝑛 𝐹𝑜𝑟𝑤𝑎𝑟𝑑 𝐴𝑐𝑡𝑖𝑣𝑒. Use +𝑉𝐷𝐷 = 9 𝑉 and −𝑉𝑆𝑆 = −9 𝑉. Clearly show your steps.

Design Suggestion for Part A.
1. Derive the expression for 𝑅𝑖𝑑 (ignore 𝑟𝑜 of Q1 and Q2.). Replace the small signal parameter(s) with “dc currents”, “resistors”, “𝑉𝑡ℎ“, “𝛽”, “𝑉𝐴“, etc. and simplify the expressions to the extent possible (e.g., manipulate the expressions and then replace 𝑉𝐴 = 100 𝑉, 𝛽 = 200, etc.). The 𝑅𝑖𝑑 design specification will let you find an upper limit for Q1 (and Q2) dc collector current, 𝐼𝐶1(= 𝐼𝐶2).
2. The total power dissipation is 𝑃𝑇𝑂𝑇𝐴𝐿 = 𝑃𝑉𝐷𝐷 + 𝑃𝑉𝑆𝑆 = 9𝑉 ∗ (𝐼𝑉𝐷𝐷 + 𝐼𝑉𝑆𝑆). Here, 𝐼𝑉𝐷𝐷 is the sum of all dc currents leaving the +𝑉𝐷𝐷 and 𝐼𝑉𝑆𝑆 is the sum of all dc currents entering the −𝑉𝑆𝑆. In
𝑃𝑇𝑂𝑇𝐴𝐿 write 𝐼𝑉𝐷𝐷 and 𝐼𝑉𝑆𝑆 in terms of Q1 (or Q2) collector currents (ignore the current on the reference current generation branch formed by 𝑅1 and 𝑄4). The 𝑃𝑇𝑂𝑇𝐴𝐿 design specification will let you find another upper limit for 𝐼𝐶1(= 𝐼𝐶2).
3. Derive the expressions for 𝐴𝑑 and 𝐴𝑐𝑚. (When deriving 𝐴𝑑, include 𝑟𝑜 of Q1 or Q2. When deriving 𝐴𝑐𝑚 ignore 𝑟𝑜 of Q1 and Q2 but include 𝑟𝑜 of Q3.). Replace the small signal parameter(s) with “dc currents”, “resistors”, “𝑉𝑡ℎ“, “𝛽”, “𝑉𝐴“, etc. and simplify the expressions to the extent possible
(e.g., manipulate the expressions and then replace 𝑉𝐴 = 100 𝑉, 𝛽 = 200, etc.). The 𝐴𝑑 and 𝐴𝑐𝑚 design specifications will let you respectively find lower and upper limits for the product 𝑅𝐶 ∗ 𝐼𝐶1.
4. Consider the forward–active region requirement of Q1 (or Q2). For 𝑉𝐶𝑀 = 0 𝑉, find another upper limit for the product 𝑅𝐶 ∗ 𝐼𝐶1.
5. Consider the upper limits for 𝐼𝐶1 to pick an 𝐼𝐶1. Find 𝑅1 based on the value you pick for 𝐼𝐶1. Then use the upper and lower limits for 𝑅𝐶 ∗ 𝐼𝐶1 to pick 𝑅𝐶.
In your simulations, use the BJT model 2N2222 of NXP, which has a SPICE model as below with 𝑉𝐴 and 𝛽 highlighted:

B. DC Analysis: In LTSpice do a DC operating point simulation (.op) with both inputs connected to ground (i.e., 𝑉𝐶𝑀 = 0 𝑉). Find the simulated DC values for 𝐼𝑅1, 𝐼𝐶3, 𝐼𝐶4, 𝐼𝐶1, 𝐼𝐶2, 𝑉𝐵3, 𝑉𝐸1,2, 𝑉𝑂1, 𝑉𝑂2. Compare them with your hand calculations. Additionally, comment on the matching between 𝐼𝑅1 𝑎𝑛𝑑 𝐼𝐶3 and comment on the theoretical vs. simulated match between 𝐼𝑅1 𝑎𝑛𝑑 𝐼𝐶3.

C. Transient Analysis: In LTSpice do a transient simulation (.tran) for 100 ms.

For differential small–signal input simulations:
Apply 𝑣𝑖𝑑 = 1 𝑚𝑉𝑝 𝑠𝑖𝑛𝑢𝑠𝑜𝑖𝑑𝑎𝑙 𝑠𝑖𝑔𝑛𝑎𝑙 𝑎𝑡 100 𝐻𝑧. [i.e., 𝑣𝑖𝑑1 = + 𝑣𝑖𝑑 2 = 0.5 𝑚𝑉 sin (2 ∗ 𝜋 ∗ 100𝐻𝑧 ∗ 𝑡)
and 𝑣𝑖𝑑2 = − 𝑣𝑖𝑑 2 = 0.5 𝑚𝑉 sin ((2 ∗ 𝜋 ∗ 100𝐻𝑧 ∗ 𝑡) + 𝜋) with DC offset = 0V. ]

For common–mode small–signal input simulations:
Apply 𝑣𝑐𝑚 = 1 𝑚𝑉𝑝 𝑠𝑖𝑛𝑢𝑠𝑜𝑖𝑑𝑎𝑙 𝑠𝑖𝑔𝑛𝑎𝑙 𝑎𝑡 100 𝐻𝑧. [i.e., 𝑣𝑖𝑐𝑚1 = 𝑣𝑖𝑐𝑚2 = 𝑣𝑐𝑚 = 1 𝑚𝑉 sin (2 ∗ 𝜋 ∗ 100𝐻𝑧 ∗ 𝑡) with DC offset = 0V.]
1. For the differential small–signal input, what is the expected emitter voltage of Q1 and Q2, 𝑣𝑒1(= 𝑣𝑒2)? Plot the simulated waveform. What is the simulated value of 𝑣𝑒1(= 𝑣𝑒2)?
2. Plot 𝑣𝑖𝑑, 𝑣𝑜𝑑(𝑣𝑜𝑑 = 𝑣𝑜2 − 𝑣𝑜1), 𝑎𝑛𝑑 𝑖𝑖𝑑. Note that 𝑖𝑖𝑑 is the base current of Q1 (𝑖𝑖𝑑 = 𝑖𝑏1).
Calculate the simulated 𝐴𝑑 = 𝑣𝑜𝑑/𝑣𝑖𝑑 and 𝑅𝑖𝑑 = 𝑣𝑖𝑑/𝑖𝑖𝑑. Compare the values with your design targets.
3. If the simulation results do not match the design constraints, tune your circuit to achieve the goals.
4. For the common–mode small–signal input, plot 𝑣𝑐𝑚 and 𝑣𝑜𝑐𝑚. (𝑣𝑜𝑐𝑚 = 𝑣𝑜𝑐𝑚2 = 𝑣𝑜𝑐𝑚1 𝑤ℎ𝑒𝑛 𝑡ℎ𝑒 𝑖𝑛𝑝𝑢𝑡 𝑖𝑠 𝑎 𝑐𝑜𝑚𝑚𝑜𝑛 − 𝑚𝑜𝑑𝑒 𝑠𝑖𝑔𝑛𝑎𝑙)