Q1.A (10 pts) Consider the cross–talk effect in a multi–layer interconnect structure shown in the following figure. Assume the metal layers that are routed on layers n–1 and n+1 are quiet (no switching activity). When A is switching from VDD voltage level to 0 voltage level, for the following different switching activities, please provide the total effective capacitance Ceff (A) seen by A. Provide detailed explanations for your answers.

1. When B is switching opposite A and C is constant
2. When B and C are switching with A
3. When B is switching with A and C is switching opposite A Activities of B and C

Ceff(A) Miller Capacitance
Factor (MCF)
Case 1
Case 2
Case 3

Q1.B (10 pts) Assume that metal 2 is used for implementing a 3mm long, 0.25um wide wire, where Ro =0.05 Ohm/o, and Cpermicron = 0.2 fF/um. Estimate the delay of a 10X inverter driving a 1X inverter at the end of the wire modeled using 3–segment –model. The unit–sized nMOS transistor has R=10K Ohm and gate capacitance can be ignored in your analysis.

Q2. (20 pts) Consider a sequential circuit synchronized by positive edge triggered flip–flops as below. The clock period is T=15. The setup time for both flip–flops is 1. The hold time for both flip–flops is 2. Assume that the clock–to–q delay for both Flip–flops is 2. Answer the following questions.
Clock Net
a) (10 pts) Assume that the clock signal (positive edge) arrival times at flip–flops 1 and 2 are same. Please show the maximum and the minimum allowed delays for the combinational logic circuit so that both setup time (Max–delay) and hold time (Min–delay) constraints are satisfied.
b) (10 pts) Assume that the clock signal (positive edge) arrival time at flip–flop–1 is t1=
k•T+1, where k is an integer. The clock signal (positive edge) arrival time at flip–flop–2 is t2=k•T+3, where k is an integer. Please find the maximum and the minimum allowed delays for the combinational logic circuit so that both setup time (Max–delay) and hold time (Min–delay) constraints are satisfied.

Q3. (20 pts) Consider an SRAM cell design shown below and answer the following questions. a) (5 pts) Assume we want to read data from this SRAM cell, what are the necessary steps we should follow to assure a correct data read? If data 1 is stored in node A, during the read operation, which transistors are active? Please draw the current flow direction on the schematic.
b) (5 pts) Assume we want to write data 0 to node A of this SRAM cell, what are the
necessary steps we should follow to assure a correct data read? During the write operation, which transistors will be active? Please draw the current flow direction on the schematic.
c) (5 pts) To correctly perform the read and write operations for the SRAM cell, how should we determine the sizes of all the six transistors (please use S: strong, M: medium, and W: weak to indicate their sizes in the table)?
d) (5 pts) If we make the transistor size of N1<< size of N2, and size of N3<< size of N4, will this impact the read or write operation, or both?

Q4.A (10pts) Consider the following 2–input NAND gate circuit design, calculate the delay for Y falling transition considering the following two situations (assume unit inverter has a falling delay of d=3RC), and conclude your findings when the input arrival times are known in advance:
(a) A arrives latest; (b) B arrives latest.

Q4.A Figure

Q4.B (10pts) Consider the following circuit for which we want to design an asymmetric gate without impacting the critical input–out delays significantly. Assuming that input A is most critical, show how to size the other NMOS transistor with size X. Provide detailed explanations to support your answer.

Q5. A (15pts) A 1.0 V chip has a power supply impedance of 0.01 Ohm, switching from an idle mode consuming 5W to a full–power mode consuming 10 W. The transition takes 10 clock cycles at 1 GHz clock frequency. The power supply network inductance is 0.05nH. Answer the following questions:

(1) What are the IR drops before and after the operation mode switching?

(2) How about the L di/dt drop after the mode switching?

(3) Assume that the ambient temperature of the system box is 60 Celsius, the chip–to–package thermal resistance is 2 Celsius/W, and package–to–ambient thermal resistance is 5 Celsius/W.
Compute the chip temperatures before and after the switching activity.

Q5.B (5pts) Consider the time–domain step response voltage waveform of a power supply node.
List the sources (e.g. on–chip, on–package, on–board capacitances) that may have caused the 1 st , 2nd and 3 rd voltage droops in the following table and provide detailed reasons for your answers.