Determine the memory structure used in your computer architecture.
You may choose to have a unified memory for both data and instructions or you may prefer a separate memory for each.
Determine the size of your proposed memory. .
Determine what instructions can access the memory and how.
In the previous milestone, you determined all the instructions that can be handled in the proposed computer architecture. In this milestone, determine what instructions can access the memory and how.
Determine the cache levels.
You may choose to have one or more cache levels. In each cache level, you have to determine if this level is a unified or a separate cache for both data and instructions. In addition, you have to select the cache size for each level.
Determine how cache works.
Determine how to locate a block in the cache, and how to choose a block to be replaced from the cache.
Processor architecture and instruction set:
Determine the processor components and the characteristics for each component.
Control Unit (CU): This component controls the unit, aka the tasks assigned to the processor. “A control unit (CU) handles all processor control signals. It directs all input and output flow, fetches code for instructions from microprograms and directs other units and models by providing control and timing signals. A CU component is considered the processor brain because it issues orders to just about everything and ensures correct instruction execution.” (Control Unit (CU), 2012).
Arithmetic Logic Unit (ALU): “Hardware that performs addition, subtraction, and usually logical operations such as AND and OR.” (Patterson, 2013).
Determine how many registers there are in your computer architecture.
Registers: 32
A-Type : 12
B-Type : 10
Type: 10
Determine the instructions that your proposed processor can handle.
Determine the instruction size.
There are many parts to account for when it comes to instruction size.
OPCODE
Destination Registers
Function
Source Registers
Shift Amount
Instruction type and format:
Determine how many instruction types your processor will support.
32-bit fixed width. Types the processor will support:
J-Type- Jump Type
R-Type- Register Type
I-Type- Immediate Type
OPCODE- Operation Code
Determine the format of each type.
J-Type:
B25 – B0 ‣ Target
B26 – B31 ‣ OPCODE
R-Type:
B5 – B0 ‣ Functions
B6 – B10 ‣ Shift
B11 – B15 ‣ Register d
B16 – B20 ‣ Register t
B21 – B25 ‣ Register s
B26 – B31 ‣ OPCODE
I-Type:
B15 – B0 ‣ Immediate
B16 – B20 ‣ Register t
B21 – B25 ‣ Register s
B26 – B31 ‣ OPCODE
Control Unit (CU). (2012, Nov 18). Retrieved from techopedia: https://www.techopedia.com/definition/2855/control-unit-cu
Designing a CPU. (n.d.). Retrieved from Princeton.edu: extension://elhekieabhbkpmcefcoobjddigjcaadp/https://www.cs.princeton.edu/courses/archive/fall09/cos126/lectures/22CPU-2×2.pdf
Patterson, D. (2013). Computer Organization and Design: The Hardware/Software Interface. In D. Patterson, Computer Organization and Design: The Hardware/Software Interface (pp. E-45). Elsevier S&T.